Renewing DHCP While Keeping a NetworkManager Connection Up

I recently changed my DNS setup on my home network and wanted to move all the clients over to the new nameserver before turning down the old one. My DHCP server was already updated to hand out the new DNS nameserver so all I needed to do was refresh the clients. Due to a few other changes in my network, I had a multi-hour file transfer going on between two machines.

Conflicted About Sysroots

A reader has trouble with two recipes used in separate images that both generate a file with the same path. This leads to a deep dive into how Yocto sysroots work and the perils of a global sysroot cache.

Monitoring GitLab on Kubernetes

If you want decent monitoring of GitLab deployed via GitLab’s helm charts, skip the built-in Prometheus config and go straight to InfluxDB. Make sure you enable InfluxDB’s UDP interface and replace the autogenerated, default retention policy with a 1h policy. Use GitLab’s Grafana dashboards by using jq to extract the dashboard node from each .json file and then changing the datasource name to match yours.

Unpacking Xilinx 7-Series Bitstreams: Part 3

In Part 2, I detailed the configuration packet format and how the programming operation is conveyed as a sequence of register writes. As we move up to the configuration memory frame layer (see layer diagram in Part 1), the construction of a Xilinx 7-series device becomes important. A major clue about this relationship comes from the Frame Address Register, a key register in any programming operation.

Unpacking Xilinx 7-Series Bitstreams: Part 2

In Part 1, I walked through the various file formats generated by Xilinx tools, the BIT file format header, and the physical interface layer of the bitstream protocol stack. In this part, I’ll dive into the gory details of the configuration packet format and how those packets control the overall programming operation.

Unpacking Xilinx 7-Series Bitstreams: Part 1

For the past few months, I’ve been writing Xilinx 7-series bitstream manipulation tools for SymbiFlow. After building a mostly-working implementation in C++, I started to wonder what a generic framework for FPGA development tools would look like. Inspired by LLVM and partly as an excuse to learn Rust, I started a new project, Gaffe, to prototype ideas. With Xilinx 7-series fresh in my mind, I chose to reimplement the bitstream parsing as a first step. While most of the bitstream format is documented in UG470 7 Series FPGA Configuration User Guide, subtle details are omitted that I hope to clarify here.

Ubiquiti EdgeRouter Lite USB Surgery

Keeping up with updates on all the devices in my home lab usually isn’t a big deal. Windows, macOS, Android, and iOS mostly take care of themselves. Ubuntu needs the occasional touch of ‘apt upgrade’ but is otherwise painless. My printer hasn’t had new firmware in over a year (there’s definitely a vuln or two that won’t ever be patched). Given the typical monotony, I was caught off guard when the firmware update on my router failed.

Snakes in a Sysroot

A reader asks how to know which Python version will be used in a recipe. The answer is a bit more complicated than it might first appear.

All About Those Caches

A reader attempts to use the os-release recipe to include build information in the generated images but it only seems to run on a clean build.

On Wiring Diagrams

After I finished rewiring the Cobra drag car’s trunk, I found myself needing to pull a fuse to do a test and not remembering which fuse was for what. Having all the fuses and relays in one panel was a huge improvement over the original wiring but clearly it was time for labels and a wiring diagram.